1. Field of the Invention
This invention relates to electrically erasable programmable read-only memories (EEPROMs) and more specifically to EEPROMs wherein individual bytes within the EEPROM can be selectively erased or the EEPROM can be flash erased.
2. Description of the Prior Art
EEPROMs are well known in the art. EEPROMs typically comprise arrays of floating gate transistors having a source, a floating gate, a drain, and a control gate. EEPROMs can either be programmed by hot electron injection or by tunneling, and are typically erased by tunneling. In some prior art EEPROMs, different transistors within the array of floating gate transistors are individually erased or erased one byte at a time. See, for example, FIG. 5d and accompanying text of U.S. Pat. No. 4,698,787, issued to Mukherjee, et al., and incorporated herein by reference. Thus, when using such an EEPROM, selected transistors can be erased without destroying the data stored in other transistors. Unfortunately, erasing such an EEPROM is time-consuming.
Other types of EEPROMs can be flash-erased, i.e., the entire array is erased simultaneously. An example of a flash-erase EEPROM is discussed in U.S. Pat. No. 4,531,203 issued to Masuoka et al., incorporated herein by reference. Also see "A 128K Flash EEPROM Using Double-Polysilicon Technology" by G. Samachisa et al., IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, incorporated herein by reference, and FIG. 5b and accompanying text of the Mukherjee patent. Advantageously, a typical flash EEPROM takes less time to erase than an EEPROM that is erased a bit (or byte) at a time. However, individual bits or bytes in such an EEPROM cannot be erased without erasing the entire EEPROM.